Dr. José Ernesto Rayas Sánchez

Departamento de Electrónica, Sistemas e Informática
erayas@iteso.mx
Tel. 3669 3598  Ext. 3096
Oficina: T314
Sitio web

Doctor en Ingeniería Eléctrica por la Universidad McMaster, Hamilton en Ontario, Canadá. Maestro en Ciencias con especialidad en Sistemas Electrónicos, por el Instituto Tecnológico y de Estudios Superiores de Monterrey (ITESM) en Monterrey, México, e ingeniero en Electrónica por el Instituto Tecnológico y de Estudios Superiores de Occidente (ITESO) en Guadalajara, México.

Ha sido profesor en ITESO desde 1985, promovido en 1989 a la categoría de Profesor Titular del ITESO, y distinguido como Profesor Numerario desde 2005. Actualmente dirige en ITESO al Grupo de Investigación en Ingeniería Asistida por Computadora de Circuitos y Sistemas (CAECAS) y durante 2013-2019 fungió como Coordinador del Doctorado en Ciencias de la Ingeniería del ITESO.

Es miembro del comité editorial de las siguientes revistas: IEEE Transactions on Microwave Theory and Techniques, IEEE Transactions on Antennas and Propagation, IEEE Microwave and Wireless Components Letters, IET Microwaves, Antennas & Propagation Journal, International Journal of RF and Microwave Computer-Aided Engineering y de la International Journal of Numerical Modelling: Electronic Networks, Devices and Fields. Es miembro del Comité del Programa Técnico del Simposium Internacional de Microondas del IEEE (MTT-IMS). Fue presidente (2018-2019) y vice-presidente (2016-2017) del IEEE MTT-1 on CAD (Technical Committee on Computer Aided Design of the IEEE Microwave Theory and Techniques Society). Fue el coordinador general del First IEEE MTT-S Int. Microwave Workshop Series in Region 9 (IMWS2009-R9) on Signal Integrity and High-Speed Interconnects (Guadalajara, México, Feb. 2009), así como presidente general (General Chair) del First IEEE MTT-S Latin America Microwave Conference (LAMC-2016, Puerto Vallarta, Mexico, Dic. 10-12, 2016). Desde 2013 es Coordinador para Latinoamérica del IEEE MTT-S. Desde 2019 es el representante de la MTT-S ante el Consejo del IEEE en Automatización del Diseño Electrónico (IEEE Council on Electronic Design Automation, CEDA). Actualmente es miembro del Sistema Nacional de Investigadores (SNI), Nivel II.

Su línea de investigación está enfocada hacia el desarrollo de métodos asistidos por la computadora (CAD) para el modelado, diseño y optimización de circuitos y dispositivos electrónicos de alta velocidad (incluyendo circuitos de RF, microonda e inalámbricos), empleando simuladores de alta precisión y alto costo computacional, tema sobre el cual ha producido numerosas publicaciones científicas internacionales. Sus trabajos han recibido más de 1,900 citas de la comunidad científica.

Campo de especialidad
Diseño basado en electromagnetismo
Diseño de circuitos RF y microonda
Interconexiones de alta velocidad
Integridad de señales e integridad de potencia
Métodos de CAD para circuitos eléctricos
Optimización de circuitos

Proyectos de investigación
Dirección del grupo de investigación en Ingeniería Asistida por Computadora de Circuitos y Sistemas (CAECAS, Computer Aided Engineering of Circuits and Systems). 
Colaboradores en ITESO: Dr. Zabdiel Brito Brito, Dr. José Luis Chávez-Hurtado, Dr. Omar Longoria Gándara y tesistas de maestría y doctorado.
Colaboradores externos: Dr. John W. Bandler, McMaster University, Canadá; Dr. Vicente E. Boria, Universidad Politécnica de Valencia, España; Dr. Q. J. Zhang, Carleton University, Canadá; Dr. Slawomir Koziel, University of Reykjavik, Islandia; Dr. Rodrigo Camacho, Intel Labs Guadalajara, México; Dr. Francisco Rangel-Patiño, Intel Guadalajara, México; Dr. Víctor Champac, INAOE Puebla, México; Dr. Roberto Murphy, INAOE Puebla, México; Dr. Raúl Loo, CINVESTAV Guadalajara, México; Dra. Carmen Maya, CICESE Ensenada, México; Dr. Apolinar Reynoso, CICESE Ensenada, México.

Publicaciones recientes
Artículos de revista

F. J. Leal-Romo, J. E. Rayas-Sánchez, and J. L. Chávez-Hurtado, "Surrogate-based analysis and design optimization of power delivery networks," IEEE Trans. Electromagnetic Compatibility, early access version, vol. 62, 2020. (p-ISSN: 0018-9375; e-ISSN: 1558-187X; published online: 24 Mar. 2020; DOI: 10.1109/TEMC.2020.2973946)

G. Rafael-Valdivia and J. E. Rayas-Sánchez, "The second IEEE MTT-S Latin America microwave conference [Conference Report]," IEEE Microwave Magazine, vol. 21, no. 1, pp. 114-118, Jan. 2020. (p-ISSN: 1527-3342; e-ISSN: 1557-9581; published online: 26 Nov. 2019; DOI: 10.1109/MMM.2019.2945217)

A. Viveros-Wacher, J. E. Rayas-Sánchez, and Z. Brito-Brito, "Analog gross fault identification in RF circuits using neural models and constrained parameter extraction," IEEE Trans. Microwave Theory Techn., vol. 67, no. 6, pp. 2143-2150, Jun. 2019. (p-ISSN: 0018-9480; e-ISSN: 1557-9670; published online: 21 May 2019; DOI: 10.1109/TMTT.2019.2914106)

I. Lomelí-Illescas, S. A. Solis-Bustos, and J. E. Rayas-Sánchez, "A tool for the automatic generation and analysis of regular analog layout modules," Elsevier Integration - the VLSI Journal, vol. 65, pp. 81-87, Mar. 2019. (p-ISSN: 0167-9260; published online: 30 Nov. 2018; DOI: 10.1016/j.vlsi.2018.11.005)

F. E. Rangel-Patiño, A. Viveros-Wacher, J. E. Rayas-Sánchez, I. Durón-Rosales, E. A. Vega-Ochoa, N. Hakim, and E. López-Miralrio, "A holistic formulation for system margining and jitter tolerance optimization in industrial post-silicon validation," IEEE Trans. Emerging Topics Computing, vol. 8, no. 2, pp. 453-463, Apr.-Jun. 2020. (p-ISSN: 2376-4562; e-ISSN: 2168-6750; published online: 29 Sep. 2017; DOI: 10.1109/TETC.2017.2757937)

F. E. Rangel-Patiño, J. L. Chávez-Hurtado, A. Viveros-Wacher, J. E. Rayas-Sánchez, and N. Hakim, "System margining surrogate-based optimization in post-silicon validation," IEEE Trans. Microwave Theory Techn., vol. 65, no. 9, pp. 3109-3115, Sep. 2017. (p-ISSN: 0018-9480; e-ISSN: 1557-9670; published online: 30 May 2017; DOI:  10.1109/TMTT.2017.2701368)

J. E. Rayas-Sánchez and G. E. Ponchak, "The first IEEE MTT-S Latin America microwave conference [Conference Report]," IEEE Microwave Magazine, vol. 18, no. 6, pp. 128-131, Sep.-Oct. 2017. (p-ISSN: 1527-3342; e-ISSN: 1557-9581; published online: 8 August 2017; DOI: 10.1109/MMM.2017.2712067)

J. L. Chavez-Hurtado and J. E. Rayas-Sánchez, "Polynomial-based surrogate modeling of RF and microwave circuits in frequency domain exploiting the multinomial theorem," IEEE Trans. Microwave Theory Techn., vol. 64, no. 12, pp. 4371-4381, Dec. 2016. (p-ISSN: 0018-9480; e-ISSN: 1557-9670; published online: 17 Nov. 2016; DOI:  10.1109/TMTT.2016.2623902)

J. E. Rayas-Sanchez, "Power in simplicity with ASM: tracing the aggressive space mapping algorithm over two decades of development and engineering applications," IEEE Microwave Magazine, vol. 17, no. 4, pp. 64-76, Apr. 2016. (ISSN: 1527-3342; INSPEC: 15823213; published online: 7 Mar. 2016; DOI: 10.1109/MMM.2015.2514188)

J. C. Cervantes-González, J. E. Rayas-Sánchez, C. A. López, J. R. Camacho-Pérez, Z. Brito-Brito, and J. L. Chavez-Hurtado, "Space mapping optimization of handset antennas considering EM effects of mobile phone components and human body," Int. J. RF and Microwave CAE, vol. 26, no. 2, pp. 121-128, Feb. 2016. (ISSN: 1096-4290; Online ISSN: 1099-047X; published online: 21 Oct. 2015, DOI: 10.1002/mmce.20945)

J. E. Rayas-Sánchez, J. L. Chavez-Hurtado, and Z. Brito-Brito, "Design optimization of full-wave EM models by low-order low-dimension polynomial surrogate functionals," Int. J. Numerical Modelling: Electron. Networks, Dev. Fields., vol. 30, no. 3-4, e2094, May-Aug. 2017. (ISSN: 0894-3370; Online ISSN: 1099-1204; published online: 13 Sep. 2015, DOI: 10.1002/jnm.2094)

L. M. Aguilar-Lobo, J. R. Loo-Yau, J. E. Rayas-Sánchez, S. Ortega-Cisneros, P. Moreno, and J. A. Reynoso-Hernández, "Application of the NARX neural network as a digital predistortion technique for linearizing microwave power amplifiers," Microwave and Optical Technology Letters, vol. 57, no. 9, pp. 2137-2142, Sep. 2015. (ISSN: 0895-2477; DOI: 10.1002/mop.29281)

J. E. Rayas-Sánchez, D. Pasquet, B. Szendrenyi, and M. S. Gupta, "MTT-S Mexico trip: addressing the RF and microwave community in Mexico," IEEE Microwave Magazine, vol. 16, no. 7, pp. 104-107, Aug. 2015. (ISSN: 1527-3342; DOI: 10.1109/MMM.2015.2431240)

R. Murphy, R. Torres, J. E. Rayas-Sánchez, A. Reynoso, M. Maya-Sánchez, A. Henze, A. Zozaya, P. del Pino, J. Pena, and G. Rafael-Valdivia, "R&D in Latin America: RF and microwave research in Latin America," IEEE Microwave Magazine, vol. 15, no. 3, pp. 97-103, May 2014. (ISSN: 1527-3342; INSPEC:14209986; DOI: 10.1109/MMM.2014.2302660)

V. Gutiérrez-Ayala and J. E. Rayas-Sánchez, "Neural input space mapping optimization based on nonlinear two-layer perceptrons with optimized nonlinearity," Int. J. RF and Microwave CAE, vol. 20, no. 5, pp. 512-526, Sep. 2010. (ISSN: 1096-4290; Online ISSN: 1099-047X; IDS: 642LB; DOI: 10.1002/mmce.20457)

Capítulos de libro
J. E. Rayas-Sánchez, "Artificial neural networks and space mapping for EM-based modeling and design of microwave circuits," in Surrogate-Based Modeling and Optimization: Applications in Engineering, S. Koziel and L. Leifsson, Ed. New York, NY: Springer, 2013, ch. 7, pp. 147-169.

J. E. Rayas-Sánchez, "Neural space mapping methods for EM-based yield estimation," in Simulation-Driven Design Optimization and Modeling for Microwave Engineering, S. Koziel, X-S Yang, and Q. J. Zhang, Ed. London, England: Imperial College Press, 2013, ch. 11, pp. 271-310.

Artículos de congreso

R. Loera-Díaz and J. E. Rayas-Sánchez, "An objective function formulation for circuit parameter extraction based on the Kullback-Leibler distance," in IEEE MTT-S Int. Microwave Symp. Dig., Los Angeles, CA, Jun. 2020, pp. 80-82. (ISSN: 0149-645X; ISSN-e: 2576-7216; ISBN: 978-1-7281-6816-6; e-ISBN: 978-1-7281-6815-9; INSPEC: *; DOI: 10.1109/IMS30576.2020.9224002)

B. Mercado-Casillas and J. E. Rayas-Sánchez, "Towards signal-power integrity analysis by efficient power delivery network lumped models obtained from parameter extraction," in Int. Conf. Electrical Performance of Electronic Packaging and Systems (EPEPS 2019), Montreal, Canada, Oct. 2019, pp. 1-3. (ISSN: 2165-4107; eISSN: 2165-4115; ISBN: 978-1-7281-4586-0; e-ISBN: 978-1-7281-4585-3; INSPEC: 19569119; DOI: 10.1109/EPEPS47316.2019.193214)

J. E. Rayas-Sánchez and Z. Brito-Brito, "Applications of Broyden-based input space mapping to modeling and design optimization in high-tech companies in Mexico," in European Microwave Conf. (EuMC-2019), Paris, France, Oct. 2019, pp. 272-275. (p-ISBN: 978-1-7281-1798-0; e-ISBN: 978-2-87487-055-2; INSPEC: 19173832; DOI: 10.23919/EuMC.2019.8910799)

R. J. Sánchez-Mesa, D. M. Cortés-Hernández, J. E. Rayas-Sánchez, Z. Brito-Brito, and L. de-la-Mora-Hernández, "EM parametric study of length matching elements exploiting an ANSYS HFSS Matlab-Python driver," in IEEE MTT-S Latin America Microwave Conf. (LAMC-2018), Arequipa, Peru, Dec. 2018, pp. 1-3. (ISBN: 978-1-5386-7334-8; e-ISBN: 978-1-5386-7333-1; INSPEC: 18620760; DOI: 10.1109/LAMC.2018.8699050)

F. Leal-Romo, J. L. Chávez-Hurtado, and J. E. Rayas-Sánchez, "Selecting surrogate-based modeling techniques for power integrity analysis," in IEEE MTT-S Latin America Microwave Conf. (LAMC-2018), Arequipa, Peru, Dec. 2018, pp. 1-3. (ISBN: 978-1-5386-7334-8; e-ISBN: 978-1-5386-7333-1; INSPEC: 18635587; DOI: 10.1109/LAMC.2018.8699021)

R. J. Sánchez-Mesa, D. M. Cortés-Hernández, B. Gálvez-Sahagún, J. E. Rayas-Sánchez, and Z. Brito-Brito, "A novel high-performance length matching element for high-speed interconnect differential channels," in IEEE MTT-S Latin America Microwave Conf. (LAMC-2018), Arequipa, Peru, Dec. 2018, pp. 1-3. (ISBN: 978-1-5386-7334-8; e-ISBN: 978-1-5386-7333-1; INSPEC: 18635570; DOI: 10.1109/LAMC.2018.8699027)

F. E. Rangel-Patiño, J. E. Rayas-Sánchez, and N. Hakim, "Transmitter and receiver equalizers optimization methodologies for high-speed links in industrial computer platforms post-silicon validation," in Int. Test Conf. (ITC-2018), Phoenix, AZ, Oct. 2018, pp. 1-10. (p-ISSN: 1089-3539; e-ISSN: 2378-2250; ISBN: 978-1-5386-8383-5; e-ISBN: 978-1-5386-8382-8; INSPEC: 18429815; DOI: 10.1109/TEST.2018.8624794)

J. E. Rayas-Sánchez, F. E. Rangel-Patiño, A. Viveros-Wacher, J. L. Chávez-Hurtado, J. R. del-Rey, F. Leal-Romo, and Z. Brito-Brito, "Industry-oriented research projects on computer-aided design of high-frequency circuits and systems at ITESO Mexico," in European Microwave Conf. (EuMC-2018), Madrid, Spain, Sep. 2018, pp. 588-591. (p-ISBN: 978-1-5386-5285-5; e-ISBN: 978-2-87487-051-4;  https://www.researchgate.net/publication/328346442)

A. Viveros-Wacher and J. E. Rayas-Sánchez, "Analog fault identification in RF circuits using artificial neural networks and constrained parameter extraction," in IEEE MTT-S Int. Conf. Num. EM Mutiphysics Modeling Opt. (NEMO-2018), Reykjavik, Iceland, Aug. 2018, pp. 1-3. (ISBN: 978-1-5386-5205-3; e-ISBN: 978-1-5386-5204-6; INSPEC: 18197592; DOI: 10.1109/NEMO.2018.8503117)

F. E. Rangel-Patiño, J. E. Rayas-Sánchez, A. Viveros-Wacher, E. A. Vega-Ochoa, and N. Hakim, "High-speed links receiver optimization in post-silicon validation exploiting Broyden-based input space mapping," in IEEE MTT-S Int. Conf. Num. EM Mutiphysics Modeling Opt. (NEMO-2018), Reykjavik, Iceland, Aug. 2018, pp. 1-3. (ISBN: 978-1-5386-5205-3; e-ISBN: 978-1-5386-5204-6; INSPEC: 18197574; DOI: 10.1109/NEMO.2018.8503099)

F. Leal-Romo, J. L. Silva-Perales, C. López-Limón, and J. E. Rayas-Sánchez, "Optimizing phase settings of high-frequency voltage regulators for power delivery applications," in IEEE Workshop on Signal and Power Integrity (SPI-2018), Brest France, May 2018, pp. 1-4. (ISBN: 978-1-5386-2300-8; e-ISBN: 978-1-5386-2299-5; INSPEC: 17895920; DOI: 10.1109/SaPIW.2018.8401657)

F. E. Rangel-Patiño, J. E. Rayas-Sánchez, E. A. Vega-Ochoa, and N. Hakim, "Direct optimization of a PCI Express link equalization in industrial post-silicon validation," in IEEE Latin American Test Symp.  (LATS 2018), Sao Paulo, Brazil, Mar. 2018, pp. 1-6. (ISSN: 2373-0862; ISBN: 978-1-5386-1473-0; e-ISBN: 978-1-5386-1472-3; INSPEC: 17749128; DOI: 10.1109/LATW.2018.8347238)

A. Viveros-Wacher, R. Baca-Baylón, F. E. Rangel-Patiño, M. A. Dávalos-Santana, E. A. Vega-Ochoa, and J. E. Rayas-Sánchez, "Jitter tolerance acceleration using the golden section optimization technique," in IEEE Latin American Symp. Circuits and Systems Dig. (LASCAS 2018), Puerto Vallarta, Mexico, Feb. 2018, pp. 1-4. (ISSN: 2473-4667; ISBN: 978-1-5386-2312-1; e-ISBN: 978-1-5386-2311-4; INSPEC: 17895466; DOI: 10.1109/LASCAS.2018.8399908)

F. Leal-Romo, M. Cabrera-Gómez, J. E. Rayas-Sánchez, and D. M. García-Mora, "Design optimization of a planar spiral inductor using space mapping," in Int. Conf. Electrical Performance of Electronic Packaging and Systems (EPEPS 2017), San Jose, CA, Oct. 2017, pp. 1-3. (ISSN: 2165-4115; ISBN: 978-1-5386-3632-9; e-ISBN: 978-1-5386-3631-2; INSPEC: 17669457; DOI: 10.1109/EPEPS.2017.8329706)

F. Rangel-Patino, J. L. Chávez-Hurtado, A. Viveros-Wacher, J. E. Rayas-Sánchez, and N. Hakim, "Eye diagram system margining surrogate-based optimization in a server silicon validation platform," in European Microwave Conf. (EuMC-2017), Nuremberg, Germany, Oct. 2017, pp. 540-543. (ISBN: 978-1-5386-3964-1; e-ISBN: 978-2-87487-047-7; https://www.researchgate.net/publication/323571676)

J. E. Rayas-Sánchez and Z. Brito-Brito, "Academic and industrial research activities on RF and microwaves in Latin America: an overview," in European Microwave Conf. (EuMC-2017), Nuremberg, Germany, Oct. 2017, pp. 536-539. (ISBN: 978-1-5386-3964-1; e-ISBN: 978-2-87487-047-7; https://www.researchgate.net/publication/323571599)

J. E. Rayas-Sánchez, "A historical account and technical reassessment of the Broyden-based input space mapping optimization algorithm," in IEEE MTT-S Int. Microwave Symp. Dig., Honolulu, HI, Jun. 2017, pp. 1495-1497. (ISBN: 978-1-5090-6361-1; e-ISBN: 978-1-5090-6360-4; INSPEC: 17225293; DOI: 10.1109/MWSYM.2017.8058906)

A. Corres-Matamoros, E. Martínez-Guerrero, and J. E. Rayas-Sánchez, "Design and validation of a portable radio-frequency diathermy prototype," in Int. Caribbean Conf. Devices, Circuits, and Systems (ICCDCS-2017), Cozumel, Mexico, Jun. 2017, pp. 93-96. (e-ISSN: 2165-3550; p-ISBN: 978-1-5386-1963-6; e-ISBN: 978-1-5386-1962-9; INSPEC: 16996066; DOI: 10.1109/ICCDCS.2017.7959710)

I. Duron-Rosales, F. Rangel-Patino, J. E. Rayas-Sánchez, J. L. Chávez-Hurtado, and N. Hakim, "Reconfigurable FIR filter coefficient optimization in post-silicon validation to improve eye diagram for optical interconnects," in Int. Caribbean Conf. Devices, Circuits, and Systems (ICCDCS-2017), Cozumel, Mexico, Jun. 2017, pp. 85-88. (e-ISSN: 2165-3550; p-ISBN: 978-1-5386-1963-6; e-ISBN: 978-1-5386-1962-9; INSPEC: 16996086; DOI: 10.1109/ICCDCS.2017.7959697)

A. Corres-Matamoros, E. Martínez-Guerrero, and J. E. Rayas-Sánchez, "A programmable CMOS voltage controlled ring oscillator for radio-frequency diathermy on-chip circuit," in Int. Caribbean Conf. Devices, Circuits, and Systems (ICCDCS-2017), Cozumel, Mexico, Jun. 2017, pp. 65-68. (e-ISSN: 2165-3550; p-ISBN: 978-1-5386-1963-6; e-ISBN: 978-1-5386-1962-9; INSPEC: 16996077; DOI: 10.1109/ICCDCS.2017.7959721)

I. Lomelí-Illescas, S. A. Solis-Bustos, and J. E. Rayas-Sánchez, "Analysis of the implications of stacked devices in nano-scale technologies for analog applications," in IEEE Latin American Test Symp. (LATS-2017), Bogota, Colombia, Mar. 2017, pp. 1-4. (ISBN: 978-1-5386-0416-8; e-ISBN: 978-1-5386-0415-1; INSPEC: 16837112; DOI: 10.1109/LATW.2017.7906750)

F. Leal-Romo, J. E. Rayas-Sánchez, and J. He, "Design of experiments implementation towards optimization of power distribution networks," in IEEE Latin American Symp. Circuits and Systems Dig. (LASCAS 2017), Bariloche, Argentina, Feb. 2017, pp. 1-4. (ISSN: 2473-4667; ISBN: 978-1-5090-5860-0; e-ISBN: 978-1-5090-5859-4 INSPEC: 16964408; DOI: 10.1109/LASCAS.2017.7948102)

A. Viveros-Wacher and J. E. Rayas-Sánchez, "Eye diagram optimization based on design of experiments (DoE) to accelerate industrial testing of high speed links," in IEEE MTT-S Latin America Microwave Conf. (LAMC-2016), Puerto Vallarta, Mexico, Dec. 2016, pp. 1-3. (ISBN: 978-1-5090-4288-3; e-ISBN: 978-1-5090-4287-6; INSPEC: 16670752; DOI: 10.1109/LAMC.2016.7851249)

F. Rangel-Patino, A. Viveros-Wacher, J. E. Rayas-Sánchez, E. A. Vega-Ochoa, I. Duron-Rosales, and N. Hakim, "A holistic methodology for system margining and jitter tolerance optimization in post-silicon validation," in IEEE MTT-S Latin America Microwave Conf. (LAMC-2016), Puerto Vallarta, Mexico, Dec. 2016, pp. 1-4. (ISBN: 978-1-5090-4288-3; e-ISBN: 978-1-5090-4287-6; INSPEC: 16670749; DOI: 10.1109/LAMC.2016.7851268)

J. R. del-Rey, Z. Brito-Brito, J. E. Rayas-Sánchez, and N. Izquierdo, "Temperature effects in automotive-grade high speed interconnects," in IEEE MTT-S Latin America Microwave Conf. (LAMC-2016), Puerto Vallarta, Mexico, Dec. 2016, pp. 1-4. (ISBN: 978-1-5090-4288-3; e-ISBN: 978-1-5090-4287-6; INSPEC: 16670767; DOI: 10.1109/LAMC.2016.7851273)

J. L. Chávez-Hurtado, J. E. Rayas-Sánchez, and Z. Brito-Brito, "Multiphysics polynomial-based surrogate modeling of microwave structures in frequency domain," in IEEE MTT-S Latin America Microwave Conf. (LAMC-2016), Puerto Vallarta, Mexico, Dec. 2016, pp. 1-3. (ISBN: 978-1-5090-4288-3; e-ISBN: 978-1-5090-4287-6; INSPEC: 16670760; DOI: 10.1109/LAMC.2016.7851279)

 I. Lomelí-Illescas, S. A. Solis-Bustos, V. H. Martínez-Sánchez, and J. E. Rayas-Sánchez, "Synthesis tool for automatic layout generation of analog structures," in IEEE ANDESCON Proc., Arequipa, Peru, Oct. 2016, pp. 1-4. (ISBN: 978-1-5090-2532-9; e-ISBN: 978-1-5090-2533-6; INSPEC: 16650408; DOI: 10.1109/ANDESCON.2016.7836218)

J. L. Chávez-Hurtado and J. E. Rayas-Sánchez, "Polynomial-based surrogate modeling of microwave structures in frequency domain exploiting the multinomial theorem," in IEEE MTT-S Int. Microwave Symp. Dig., San Francisco, CA, May 2016, pp. 1-3. (ISBN: 978-1-5090-0699-1; e-ISBN: 978-1-5090-0698-4; INSPEC: 16213637; DOI: 10.1109/MWSYM.2016.7540398)

J. E. Rayas-Sánchez, J. L. Chávez-Hurtado, and Z. Brito-Brito, "Enhanced formulation for polynomial-based surrogate modeling of microwave structures in frequency domain," in IEEE MTT-S Int. Conf. Num. EM Mutiphysics Modeling Opt. RF, Microw., Terahertz App. (NEMO-2015), Ottawa, Canada, Aug. 2015, pp. 1-3. (ISBN: 978-1-4799-6811-4; e-ISBN: 978-1-4799-6810-7; INSPEC: 15805348; DOI: 10.1109/NEMO.2015.7415094)

Z. Brito-Brito, J. E. Rayas-Sánchez, and J. L. Chávez-Hurtado, "Enhanced procedure to setup the simulation bounding box and the meshing scheme of a 3D finite element EM simulator for planar microwave structures," in IEEE MTT-S Int. Microwave Symp. Dig., Phoenix, AZ, May 2015, pp. 1-3. (ISBN: 978-1-4799-8274-5; INSPEC: 15326132; DOI: 10.1109/MWSYM.2015.7166960)

J. Rafael del-Rey, Z. Brito-Brito, and J. E. Rayas-Sánchez, "Impedance matching analysis and EMC validation of a low-cost PCB differential interconnect," in IEEE Latin-American Test Symp. (LATS-2015), Puerto Vallarta, Mexico, Mar. 2015, pp. 1-5. (ISSN: 2373-0862; INSPEC: 15111168; DOI: 10.1109/LATW.2015.7102514)

 J. L. Chávez-Hurtado, J. E. Rayas-Sánchez, and Z. Brito-Brito, "Reliable full-wave EM simulation of a single-layer SIW interconnect with transitions to microstrip lines," in COMSOL Conf., Boston, MA, Oct. 2014, pp. 1-5. (DOI: 10.13140/RG.2.1.2579.1445)

L. M. Aguilar-Lobo, A. Garcia-Osorio, J. R. Loo-Yau, S. Ortega-Cisneros, P. Moreno, J. E. Rayas-Sánchez, and J. A. Reynoso-Hernández, "A digital predistortion technique based on a NARX network to linearize GaN class F power amplifiers," in IEEE Int. Midwest Symp. Circuits Syst., College Station, TX, Aug. 2014, poster

L. M. Aguilar-Lobo, A. Garcia-Osorio, J. R. Loo-Yau, S. Ortega-Cisneros, P. Moreno, J. E. Rayas-Sánchez, and J. A. Reynoso-Hernández, "A digital predistortion technique based on a NARX network to linearize GaN class F power amplifiers," in IEEE Int. Midwest Symp. Circuits Syst., College Station, TX, Aug. 2014, pp. 717-720. (p-ISSN: 1548-3746; p-ISBN: 978-1-4799-4134-6; e-ISBN: 978-1-4799-4132-2; INSPEC: 14631538; DOI: 10.1109/MWSCAS.2014.6908515)

J. E. Rayas-Sánchez and Z. Brito-Brito, "Research activities on computer-aided modeling, design and optimization of RF and microwave circuits at ITESO Mexico" in IEEE MTT-S Int. Microwave Symp. Dig., Tampa, FL, Jun. 2014, pp. 1-3. (ISSN: 0149-645X; ISBN: 978-1-4799-3868-1; INSPEC: 14432494; DOI: 10.1109/MWSYM.2014.6848342)

Z. Brito-Brito, J. E. Rayas-Sánchez, J. C. Cervantes-González, and C. A. López, "Impact of 3D EM model configuration on the direct optimization of microstrip structures," in COMSOL Conf., Boston, MA, Oct. 2013, pp. 1-5. (DOI: 10.13140/RG.2.1.3889.8641)

J. C. Cervantes-González, C. A. López, J. E. Rayas-Sánchez, Z. Brito-Brito, and G. Hernández-Sosa, "Return-loss minimization of package interconnects through input space mapping using FEM-based models," in Proc. SBMO/IEEE MTT-S Int. Microwave Optoelectronics Conf. (IMOC-2013), Rio de Janeiro, Brazil, Aug. 2013, pp. 1-4. (ISBN: 978-1-4799-1397-8; INSPEC: 13878011; DOI: 10.1109/IMOC.2013.6646607)

J. E. Rayas-Sánchez, Z. Brito-Brito, J. C. Cervantes-González, and C. A. López, "Systematic configuration of coarsely discretized 3D EM solvers for reliable and fast simulation of high-frequency planar structures," in IEEE Latin American Symp. Circuits and Systems Dig. (LASCAS 2013), Cuzco, Peru, Feb. 2013, pp. 1-4. (ISSN: 2473-4667; p-ISBN: 978-1-4673-4897-3; DOI: 10.1109/LASCAS.2013.6519093)

D. Becerra-Pérez and J. E. Rayas-Sánchez, "Optimization of the stub-alternated and serpentine microstrip structures to minimize far-end crosstalk," in IEEE Conf. Electrical Performance of Electronic Packaging and Systems (EPEPS 2012), Tempe, AZ, Oct. 2012, pp. 109-112. (ISSN: 2165-4115; e-ISBN: 978-1-4673-2537-0; p-ISBN: 978-1-4673-2539-4; INSPEC: 13308359; DOI: 10.1109/EPEPS.2012.6457854)

 J. E. Rayas-Sánchez, J. Aguilar-Torrentera, Z. Brito-Brito, J. C. Cervantes-González, and C. A. López, "EM simulation of a low-pass filter based on a microstrip defected ground structure," in COMSOL Conf., Boston, MA, Oct. 2012, pp. 1-6. (DOI: 10.13140/RG.2.1.1717.9606)

J. E. Rayas-Sánchez and E. Estrada-Arámbula, "EM-based design optimization of microstrip lines traversing a rectangular gap in the reference plane," in Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Seville, Spain, Sep. 2012, pp. 197-200. (p-ISBN: 978-1-4673-0685-0; e-ISBN: 978-1-4673-0686-7; INSPEC: 13101579; DOI: 10.1109/SMACD.2012.6339451)

J. E. Rayas-Sánchez and Q. J. Zhang, "On knowledge-based neural networks and neuro-space mapping," in IEEE MTT-S Int. Microwave Symp. Dig., Montreal, Canada, Jun. 2012, pp. 1-3. (ISSN: 0149-645X; E-ISBN: 978-1-4673-1086-4; P-ISBN: 978-1-4673-1085-7; DOI: 10.1109/MWSYM.2011.5972954)

F. Leal-Romo, R. Moreyra-González, and J. E. Rayas-Sánchez, "HFSS automated driver based on non-GUI scripting for EM-based design of high-frequency circuits," in IEEE Latin American Symp. Circuits and Systems (LASCAS 2012), Playa del Carmen, Mexico, Feb. 2012, pp. 1-4. (ISSN: 2473-4667; p-ISBN: 978-1-4673-1207-3; e-ISBN: 978-1-4673-1208-0; INSPEC: 12674909; DOI: 10.1109/LASCAS.2012.6180324)

J. E. Rayas-Sánchez and N. Vargas-Chávez, "A linear regression inverse space mapping algorithm for EM-based design optimization of microwave circuits," in IEEE MTT-S Int. Microwave Symp. Dig., Baltimore, MD, Jun. 2011, pp. 1-4. (ISSN: 0149-645X; E-ISBN: 978-1-61284-756-6; P-ISBN: 978-1-61284-754-2; INSPEC: 12180836; DOI: 10.1109/MWSYM.2011.5972954)

J. E. Rayas-Sánchez, "EM-based design optimization of RF and microwave circuits using functional surrogate models," in IEEE MTT-S Int. Microwave Symp. Workshop Notes and Short Courses, Baltimore, MD, Jun. 2011

D. Becerra-Pérez and J. E. Rayas-Sánchez, "Driving Sonnet through a Python-based interface," in Int. Review of Progress in Applied Computational Electromagnetics (ACES 2011), Williamsburg, VA, Mar. 2011, pp. 412-417

J. E. Rayas-Sánchez and N. Vargas-Chávez, "Design optimization of microstrip lines with via fences through surrogate modeling based on polynomial functional interpolants," in IEEE Conf. Electrical Performance of Electronic Packaging and Systems (EPEPS 2010), Austin, TX, Oct. 2010, pp. 125-128. (ISSN: 2165-4115; e-ISBN: 978-1-4244-6866-9; p-ISBN: 978-1-4244-6865-2; INSPEC: 11664332)

J. E. Rayas-Sánchez and D. E. Cordero-Baltazar, "Impact of base points distributions on the polynomial surrogate modeling of a substrate integrated waveguide with microstrip transitions," in Electronics, Robotics and Automotive Mechanics Conf. (CERMA 2010), Cuernavaca, Mexico, Sep. 2010, pp. 705-710. (P-ISBN: 978-1-4244-8149-1; INSPEC: 11761600; DOI: 10.1109/CERMA.2010.80)

J. E. Rayas-Sánchez, J. Aguilar-Torrentera and J. A. Jasso-Urzúa, "Surrogate modeling of microwave circuits using polynomial functional interpolants," in IEEE MTT-S Int. Microwave Symp. Dig., Anaheim, CA, May 2010, pp. 197-200. (ISSN: 0149-645X; E-ISBN: 978-1-4244-6057-1; P-ISBN: 978-1-4244-6056-4; INSPEC: 11453118; DOI: 10.1109/MWSYM.2010.5517648)

S. Ogurtsov, S. Koziel and J. E. Rayas-Sánchez, "Design optimization of a broadband microstrip-to-SIW transition using surrogate modeling and adaptive design specifications," in Int. Review of Progress in Applied Computational Electromagnetics (ACES 2010), Tampere, Finland, Apr. 2010, pp. 878-883

Patentes

J. E. Rayas-Sánchez (ITESO), "Método para dimensionar automáticamente una caja de simulación de cualquier circuito no radiante de alta frecuencia aplicable a cualquier simulador electromagnético," Mexican Patent Application MX/A/2015/017323 (IMPI), Dec. 15, 2015.